FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes
نویسندگان
چکیده
منابع مشابه
High-Throughput Irregular LDPC Decoder
Abstract— This paper presents a high-throughput area-efficient decoder design for the irregular Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids...
متن کاملConfigurable LDPC Decoder Architectures for Regular and Irregular Codes
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more genera...
متن کاملMulti-Rate Reconfigurable LDPC Decoder Architectures for QC-LDPC codes in High Throughput Applications
The problem at hand is to design and implement an efficient architecture for a Low Density Parity Check (LDPC) decoder. LDPC codes are widely used in digital communication for error free communications. They are known for their ability to achieve channel capacities. The algorithms explored for LDPC decoding are Log-Domain Sum-Product and Min-sum algorithm with offset/scaling. Both work on the s...
متن کاملStrategies for High-Throughput FPGA-based QC-LDPC Decoder Architecture
We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QCLDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioni...
متن کاملHigh-throughput Fpga Qc-ldpc Decoder Architecture for 5g Wireless
OF THE THESIS High-Throughput FPGA QC-LDPC Decoder Architecture for 5G Wireless by Swapnil Mhaske Thesis Director: Professor Predrag Spasojevic Wireless data traffic is expected to increase by a 1000 fold by the year 2020 with more than 50 billion devices connected to these wireless networks with peak data rates upto 10 Gb/s . The next generation of wireless cellular technology (being collectiv...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2016
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2016/v9i48/97269